efuse@3d2bc000 {
			compatible = "apple,t8103-efuses", "apple,efuses";
			reg = <0x2 0x3d2bc000 0x0 0x1000>;
			#address-cells = <1>;
			#size-cells = <1>;

			ecid: efuse@500a {
				reg = <0x500 0x8>;
			};

			atcphy1_cio3pll_dco_coarsebin0: efuse@438,19 {
				reg = <0x438 4>;
				bits = <19 6>;
			};

			atcphy1_cio3pll_dco_coarsebin1: efuse@438,25 {
				reg = <0x438 4>;
				bits = <25 6>;
			};

			atcphy1_cio3pll_dll_start_capcode: efuse@438,31 {
				reg = <0x438 4>;
				bits = <31 1>;
			};

			atcphy1_aus_cmn_shm_vreg_trim: efuse@438,14 {
				reg = <0x438 4>;
				bits = <14 5>;
			};

			atcphy1_cio3pll_dll_start_capcode_workaround: efuse@43c,0 {
				reg = <0x43c 0x4>;
				bits = <0 1>;
			};

			atcphy1_cio3pll_dtc_vreg_adjust: efuse@43c,1 {
				reg = <0x43c 0x4>;
				bits = <1 3>;
			};

			atcphy1_auspll_rodco_encap: efuse@438,7 {
				reg = <0x438 4>;
				bits = <7 2>;
			};

			atcphy1_auspll_rodco_bias_adjust: efuse@438,4 {
				reg = <0x438 4>;
				bits = <4 3>;
			};

			atcphy1_auspll_fracn_dll_start_capcode: efuse@438,12 {
				reg = <0x438 4>;
				bits = <12 2>;
			};

			atcphy1_auspll_dtc_vreg_adjust: efuse@438,9 {
				reg = <0x438 4>;
				bits = <9 3>;
			};
		};

		// ...

		atcphy0: phy@383000000 {
			compatible = "apple,t8103-atcphy";
			reg = <0x3 0x83000000 0x0 0x50000>,
				<0x3 0x80000000 0x0 0x4000>,
				<0x3 0x82a90000 0x0 0x4000>,
				<0x3 0x82a84000 0x0 0x4000>;
			reg-names = "core", "axi2af", "usb2phy",
				"pipehandler";

			#phy-cells = <1>;
			#reset-cells = <0>;

			orientation-switch;
			mode-switch;
			accessory; // TODO: this sounds wrong but is required for the mux
			power-domains = <&ps_atc0_usb>;
		};

		// ...

		atcphy1: phy@503000000 {
			compatible = "apple,t8103-atcphy";
			reg = <0x5 0x03000000 0x0 0x50000>,
				<0x5 0x0 0x0 0x4000>,
				<0x5 0x02a90000 0x0 0x4000>,
				<0x5 0x02a84000 0x0 0x4000>;
			reg-names = "core", "axi2af", "usb2phy",
				"pipehandler";

			nvmem-cells = <&atcphy1_aus_cmn_shm_vreg_trim>,
				<&atcphy1_auspll_rodco_encap>,
				<&atcphy1_auspll_rodco_bias_adjust>,
				<&atcphy1_auspll_fracn_dll_start_capcode>,
				<&atcphy1_auspll_dtc_vreg_adjust>,
				<&atcphy1_cio3pll_dco_coarsebin0>,
				<&atcphy1_cio3pll_dco_coarsebin1>,
				<&atcphy1_cio3pll_dll_start_capcode>,
				<&atcphy1_cio3pll_dtc_vreg_adjust>,
				<&atcphy1_cio3pll_dll_start_capcode_workaround>;
			nvmem-cell-names =  "aus_cmn_shm_vreg_trim",
				"auspll_rodco_encap",
				"auspll_rodco_bias_adjust",
				"auspll_fracn_dll_start_capcode",
				"auspll_dtc_vreg_adjust",
				"cio3pll_dco_coarsebin0",
				"cio3pll_dco_coarsebin1",
				"cio3pll_dll_start_capcode",
				"cio3pll_dtc_vreg_adjust",
				"cio3pll_dll_start_capcode_workaround";

			#phy-cells = <1>;
			#reset-cells = <0>;

			orientation-switch;
			mode-switch;
			accessory; // TODO: this sounds wrong but is required for the mux
			power-domains = <&ps_atc1_usb>;
		};